1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Description of the Related Art
A non-volatile memory is characterized in that data stored in that memory is not deleted even after the power thereto is turned off. In this point, the nonvolatile memory is different from a volatile memory such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like, from which data is deleted when the power thereto is turned off. Examples of the non-volatile memory include a flash memory (EEPROM) which is used for various applications such as portable phones, etc., a ferroelectric memory (FRAM) which is used in an IC card, etc., a magnetic memory (MRAM) which has been actively developed, and the like.
FIG. 1 schematically shows a structure of a flash memory cell for used in a non-volatile semiconductor storage device. A flash memory cell 10 shown in FIG. 1 has a control gate 2, a floating gate 3, a source 4, and a drain 5. Data, xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, is stored in this flash memory cell 10 according to the quantity of electrons infected in the floating gate 3. A plurality of such flash memory cells 10 are arranged into a plurality of matrix blocks each formed by mxn cells 10, and the matrix blocks are connected to one another, whereby a flash memory array (nonvolatile semiconductor storage device) is formed.
FIG. 2 shows a structure of an NOR-type flash memory, and especially, shows a relationship between an X-decoder and word lines. As shown in FIG. 2, the NOR-type flash memory includes a pair of matrix blocks BLK1 and BLK2 formed by a plurality of flash memory cells 10. In each matrix block, control gates 2 of n flash memory cells 10 in a row are connected to a corresponding one of m word lines WL1 to WLm, and drains 5 of m flash memory cells 10 in a column are connected to a corresponding one of n bit lines BL1 to BLn. In the blocks BLK1 and BLK2, all of the sources 4 of the flash memory cells 10 are connected to a single common source line S.
As shown in FIG. 2, in each block of the flash Memory array, sources 4 of the flash memory cells 10 are commonly connected to the single source line S. In such a structure, data stared in the flash memory calls 10 in one block is deleted all together and cannot be deleted from each of the flash memory cells 10, i.e., cannot be deleted on a bit-by-bit basis.
Reading, writing, and deleting of date In the flash memory array shown in FIG. 2 is now briefly described. When data stored in some of the flash memory cells 10 is read out, read signals including a control signal, an address signal, etc., are supplied from a central processing unit (CPU: not shown), or the like, externally connected to the flash memory array so that a high voltage of, for example, 5 V is applied to a control gate 2 of the flash memory cell 10, a low voltage of, for example, 1 V is applied to a drain 5 of the flash memory cell 10, and a low voltage of, for example, 0 V is applied to a source 4 of the flash memory cell 10. At this time, the magnitude of a current which flows between the source 4 and the drain 5 is sensed by a sense amplifier (not shown), thereby determining whether data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Then, the data read from the flash memory cell 10 is output outside of the flash memory, whereby a data reading operation is completed.
Writing of data in the flash memory array is performed as follows. When a control signal, an address signal, and data are supplied from a CPU or the like, which is externally connected to the flash memory array, are supplied to the flash memory array, in some of the flash memory cells 10 which is designated by the address signal, a high voltage of, for example, 12 V is applied to the control gate 2, a high voltage of, for example, 7 V is applied to the drain 5, and a low voltage of, for example, 0 V is applied to the source 4. By applying such voltages, hot electrons are generated in the vicinity of the junction of the drain 5, and the generated hot electrons are injected into the floating gate 3 due to the high voltage applied to the control gate 2. Thereafter, such a writable state is ended, and a verification operation is performed. After the writing of data in the flash memory cell 10 has been completed, if the verification operation is successful, the writing operation is completed. If the verification operation is unsuccessful, writing of the data, and the verification operation, are performed again. If the verification operation is unsuccessful again, writing of the data, and the verification operation, are further performed a predetermined number of times. If the verification operation is still unsuccessful, the CPU or the like recognizes it as a write error.
Lastly, an erasing operation of the flash memory array is described. Data in the flash memory array is erased on a block by block basis. A control signal, a block address, and a deletion command are supplied from the CPU or the like to the flash memory array so that a low voltage of, for example, xe2x88x9210 V is applied to the control gate 2, the drain 5 is floated, and a high voltage of, for example, 6 V is applied to the source 4. With application of such voltages, a high electric field is generated between the floating gate 3 and the source 4, and electrons in the control gate 2 can be taken out therefrom by means of tunneling, whereby the data is deleted.
Thereafter, such a data erasable state is ended, and a verification operation is performed similarly to that for the writing of data. If the verification operation is successful for all of the flash memory cells 10 in the block to which the deletion command is supplied, the data deletion operation is completed. If the verification is unsuccessful, deletion of the data, and the verification operation, are performed again. If the verification operation is still unsuccessful after deletion of the data, and the verification operation, has been performed a predetermined number of times, the CPU or the like recognizes it as an erase error.
In a typical flash memory array, an erase operation including a verification operation requires a longer time than a program operation including a verification operation, and a program operation including a verification operation requires a longer time than a read operation. Specifically, the read operation requires about 100 ns, the program operation including the verification operation requires about 30 xcexcs, and the erase operation including the verification operation requires about 500 mm. Thus, in the flash memory array, a considerably longer time is required for writing and erasing of data as compared with reading of data. It should be noted that, in this specification, a xe2x80x9cprogram operationxe2x80x9d in a non-volatile memory (e.g., flash memory) means writing of data in the non-volatile memory.
On the other hand, a volatile semiconductor storage device, such as a DRAM, an SRAM, etc., loses data stored therein when the power to the storage device is turned off. However, the time required for writing data in the storage device is substantially the same as that required for reading the data therefrom. For example, in an SRAM, only about 100 ns is required for completing each of a write operation and a read operation. Thus, in the SRAM, replacing of data can be completed in a considerably shorter time as compared with the time required for erasing and writing of data in the flash memory array.
FIG. 3 shows a typical memory cell of a SRAM. An SRAM memory cell 6 shown in FIG. 3 is formed by a pair of switch transistors 7 and a pair of inverters 8. Reading of data from the SRAM memory cell 6 is now described. In a read operation in the SRAM memory cell 6, in the first step, a pulse voltage is applied to a word line WL which is selected by an address signal, whereby any of the switch transistors 7 is turned on. At this time, a voltage at a BIT terminal and a voltage at a BIT# terminal are compared by a sense amplifier, thereby determining whether the data stored in the SRAM memory cell 6 is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Then, the data read from the SRAM memory cell 6 is output to an external CPU or the like, whereby the read operation is completed.
When writing data in the SRAM memory cell 6, as in the read operation, a pulse voltage is applied to a word line WL which is selected by an address signal, whereby any of the switch transistors 7 is turned on. At this time, a high voltage is applied to one of the BIT terminal and the BIT# terminal, and a low voltage is applied to the other, whereby voltages are respectively applied to nodes N1 and N2, and binary data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) is written by means of combinations of the voltages.
In a flash memory, when the CPU, which is externally connected to the flash memory, processes data, since a program operation requires a longer time, a standby time of the CPU during the program operation becomes longer. In the case of writing a large amount of data, the CPU cannot execute other operations during the program operation.
In some applications of a semiconductor storage device, data is temporarily stored in a volatile semiconductor storage device which requires a short time for a write operation, such as an SRAM, which is called a xe2x80x9cpage bufferxe2x80x9d, and then, the data is transferred to the flash memory en bloc. With such an arrangement, the time required for writing data is reduced in appearance. In such a semiconductor storage device, the CPU does not need to execute writing of data in the flash memory and therefore can secure times for other operations.
Japanese Laid-Open Publication No. 11-85609 discloses a semiconductor storage device which uses a page buffer technique where an overhead which is caused when data is transferred to a flash memory is reduced, whereby a decrease in data transfer rate is suppressed. Japanese Laid-Open Publication No. 10-283768 discloses a semiconductor storage device which uses a page buffer technique where the rate of a data write access can be increased.
Thus, in a flash memory which requires a long time for a program operation, when an external CPU processes data, a standby time of the CPU during the program operation becomes longer. Especially in the case of writing a large amount of data, the CPU cannot execute other operations for a long time during the program operation. In a conventional technique for writing data by using a pager buffer, data is temporarily stored in the page buffer, and the data is then transferred from the page buffer to a flash memory en block. With such an arrangement, the standby time of the CPU during writing of data in the flash memory is eliminated, the time required for writing data in the flash memory is reduced in appearance.
However during the transfer of data from the page buffer to the flash memory, subsequent data cannot be written in the page buffer, or the data cannot be read from the page buffer. Therefore, the page buffer cannot be used for temporarily storing other data.
In order to solve such a problem, in some applications, an SRAM is externally provided for temporarily storing data. However, in such a case, when a larger amount of data is required to be written at a high rate, the capacity of the externally-provided SRAM which is required for temporarily storing the data is increased.
Furthermore, when data in the flash memory is replaced with another, deletion of data and writing of data cannot be executed at the same time. Thus, after data in a block is erased, data is written in the cleared block on a memory cell by memory cell basis. Such a process requires a relatively long process time.
Furthermore, the above-described storage device which has the page buffer does not have a function for transferring data stored in the flash memory to the page buffer.
According to one aspect of the present invention, a semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device; a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.
In one embodiment of the present invention, the plurality of first memory arrays, the second memory array, and the data transfer section are formed on a same chip.
In another embodiment of the present invention, the plurality of semiconductor storage elements included in the first memory array are non-volatile semiconductor storage elements.
In still another embodiment of the present invention, the plurality of semiconductor storage elements included in the first memory array are volatile semiconductor storage elements.
In still another embodiment of the present invention, during a transfer of the data between at least one of the plurality of first memory arrays and the second memory array, an external device externally attached to the semiconductor storage device reads first data from or writes first data in the plurality of first memory arrays.
In still another embodiment of the present invention, during a transfer of the data between at least one of the plurality of first memory arrays and the second memory array, an external device externally attached to the semiconductor storage device reads first data from, writes first data in, or erases first data from the second memory array.
In still another embodiment of the present invention, a command to access the second memory array includes a command to access the plurality of first memory arrays.
In still another embodiment of the present invention, the data transfer section transfers the data stored in a first address in the plurality of first memory arrays to a second address in the second memory array.
In still another embodiment of the present invention, the data transfer section transfers the data stored in a second address in the second memory array to a first address in the plurality of first memory arrays.
In still another embodiment of the present invention, the data transfer section transfers the data stored in a first region in the plurality of first memory arrays to a second region in the second memory array.
In still another embodiment of the present invention, the data transfer section transfers the data stored in a second region in the second memory array to a first region in the plurality of first memory arrays.
In still another embodiment of the present invention, the data transfer section transfers all of the data stored in at least one of the plurality of first memory arrays to a particular region in the second memory array.
In still another embodiment of the present invention, the data transfer section transfers an amount of the data which is equal to the capacity of at least one of the plurality of first memory arrays to the at least one of the plurality of first memory arrays from the second memory array.
In still another embodiment of the present invention, before a transfer of the data between the plurality of first memory arrays and the second memory array, the data transfer section compares the data stored in a transfer origin address and first data stored in a transfer destination address; when the data stored in the transfer origin address is identical to the first data stored in the transfer destination address, the data transfer section does not transfer the data; and when otherwise, the data transfer section transfers the data from the transfer origin address to the transfer destination address.
In still another embodiment of the present invention, the external device accesses the plurality of first memory arrays except for the at least one of the plurality of first memory arrays during the transfer of the data between the at least one of the plurality of first memory arrays and the second memory array.
In still another embodiment of the present invention, an access by the external device to the at least one of the plurality of first memory arrays is prohibited during the transfer of the data between the at least one of the plurality of first memory arrays and the second memory array.
In still another embodiment of the present invention, a transfer of the data between the at least one of the plurality of first memory arrays and the Second memory array is interrupted by an access by the external device and the transfer of the data between the at least one of the plurality of first memory arrays and the second memory array is resumed after the access by the external device has been completed.
In still another embodiment of the present invention, while the data at being erased from a particular block in the second memory array, the plurality of first memory arrays are accessed by the external device.
In still another embodiment of the present invention, while the data is being written in a particular block in the second memory array, the plurality of first memory arrays are accessed by the external device.
In still another embodiment of the present invention, a capacity of the at least one of the plurality of the first memory arrays is equal to, multiple of, or divisional of a capacity of a block in the second memory array which can be erased en bloc.
In still another embodiment of the present invention, the plurality of first memory arrays and the second memory array exist in different memory spaces; and an access to the plurality of first memory arrays and an access to the second memory array are achieved by a single control terminal.
In still another embodiment of the present invention, the plurality of first memory arrays and the second memory array exist in a same memory space; and an access to the plurality of first memory arrays and an access to the second memory array are achieved by different control terminals.
In still another embodiment of the present invention, an access mode is switched between a first access mode where an access to the plurality of first memory arrays and an access to the second memory array are achieved by a single control terminal and a second access mode where the access to the plurality of first memory arrays and the access to the second memory array are achieved by two or more control terminals.
In still another embodiment of the present invention, the second memory array includes a plurality of banks, in each of which an erase operation and a program operation of the data and a read operation of the data can be executed separately from other banks; and the data is transferred between the plurality of banks and the plurality of first memory arrays through the data transfer section.
In still another embodiment of the present invention, during a transfer of the data between the plurality of banks and the plurality of first memory arrays, the external device executes one of reading of first data from the plurality of first memory arrays, writing of second data in the plurality of first memory arrays, and reading of third data from at least one of the plurality of banks which is not used for the transfer of the data.
In still another embodiment of the present invention, while the data is being erased from one of the plurality of banks, the external device executes one of reading of first data from the plurality of first memory arrays, writing of second data in the plurality of first memory arrays, and reading of third data from at least one of the plurality of banks in which the erasure of the data is not executed.
In still another embodiment of the present invention, while the data is being written in one of the plurality of banks, the external device executes one of reading of first data from the plurality of first memory arrays, writing of second data in the plurality of first memory arrays, and reading of third data from at least one of the plurality of banks in which the writing of the data is not executed.
In still another embodiment of the present invention, all of the data written in at least one of the plurality of first memory arrays is reset to a predetermined state.
In still another embodiment of the present invention, the at least one of the plurality of first memory arrays is reset to a value of a reset cell of the second memory array.
In still another embodiment of the present invention, after the data written in at least one of the plurality of first memory arrays is transferred to the second memory array, the at least one of the plurality of first memory arrays is reset.
In still another embodiment of the present invention, the data in at least one of the plurality of first memory arrays is protected from an overwrite.
In still another embodiment of the present invention, the data transfer section transfers the data in a first region in the second memory array to a second region in the plurality of first memory arrays when a power to the semiconductor storage device is turned on or when the semiconductor storage device returns from a power-down state to a normal active State.
In still another embodiment of the present invention, after the data is transferred from the second memory array to the plurality of first memory arrays, the transferred data in the plurality of first memory arrays are protected from an overwrite.
In still another embodiment of the present invention, an access by the external device to the plurality of first memory arrays and an access by the external device to the second memory array are performed in synchronization with a clock signal.
In still another embodiment of the present invention, a transfer status of the data between the plurality of first memory arrays and the second memory array is output to the external device.
In still another embodiment of the present invention, the semiconductor storage device further includes an input/output data bus which has a predetermined bus width, wherein allocation of bus width to the plurality of first memory arrays and the second memory array is switched between a case where one of at least one of the plurality of first memory arrays and the second memory array uses the input/output data bus and a case where both of at least one of the plurality of first memory arrays and the second memory array use the input/output data bus.
In still another embodiment of the present invention, the allocation of the bus widths to the plurality of first memory arrays and the second memory array is controlled by one of a control terminal connected to the external device and a predetermined command.
In still another embodiment of the present invention, the semiconductor storage device further includes; an input/output data bus which is used for a transfer of the data between the external device and the plurality of first memory arrays and the second memory array; and an internal data bus which is used for a transfer of the data between the plurality of first memory arrays and the second memory array, wherein a bus width of the internal data bus is greater than that of the input/output data bus.
Thus, the invention described herein makes possible the advantages of providing a semiconductor storage device which can eliminate the standby time of a device externally connected to the storage device, such as a CPU or the like, during writing of data, and which does not require an externally-provided SRAM, whereby a chip area can be reduced.
These and other advantages of the present invention will become apparent to those stilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.